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CY7C1161V18 - 18-Mbit QDR⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1161V18_4146421.PDF Datasheet

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CY7C1161V18 CY7C1161V18-300BZC CY7C1161V18-300BZI CY7C1161V18-300BZXC CY7C1161V18-300BZXI CY7C1161V18-333BZC CY7C1161V18-333BZI CY7C1161V18-333BZXC CY7C1161V18-333BZXI CY7C1163V18 CY7C1163V18-300BZC CY7C1163V18-300BZI CY7C1163V18-300BZXC CY7C1163V18-300BZXI CY7C1163V18-333BZC CY7C1163V18-333BZI CY7C1163V18-333BZXC CY7C1163V18-333BZXI CY7C1165V18 CY7C1165V18-300BZC CY7C1165V18-300BZI CY7C1165V18-300BZXC CY7C1165V18-300BZXI CY7C1165V18-333BZC CY7C1165V18-333BZI CY7C1165V18-333BZXC CY7C1165V18-333BZXI CY7C1176V18 CY7C1176V18-300BZC CY7C1176V18-300BZI CY7C1176V18-300BZXC

Description

18-Mbit QDR⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

File Size

1,011.73K / 29 Page

Maker

Cypress Semiconductor

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Part: CY7C1163KV18-400BZI

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Full text search : 18-Mbit QDR⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

Related Part Number

PART	Description	Maker
CY7C1514KV18 CY7C1514KV18-300BZXC CY7C1512KV18-300	72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 QDR SRAM, 0.45 ns, PBGA165 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.45 ns, PBGA165	Cypress Semiconductor, Corp.
CY7C1515AV18-200BZXI CY7C1526AV18-278BZXC CY7C1526	72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 QDR SRAM, 0.45 ns, PBGA165 8M X 9 QDR SRAM, 0.45 ns, PBGA165	Cypress Semiconductor, Corp. CYPRESS SEMICONDUCTOR CORP
CY7C1514V18 CY7C1514V18-200BZC CY7C1514V18-250BZC	72-Mbit QDR-II?SRAM 2-Word Burst Architecture 72-Mbit QDR-II(TM) SRAM 2-Word Burst Architecture 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture 72-MBIT QDR-II⒙ SRAM 2-WORD BURST ARCHITECTURE 72-Mbit QDR-II SRAM 2-Word Burst Architecture	CYPRESS[Cypress Semiconductor]
R1Q4A3609ABG40RS0 R1Q6A3609ABG40RS0 R1Q3A3609ABG40	1M X 36 QDR SRAM, PBGA165 1M X 36 QDR SRAM, 0.45 ns, PBGA165 36-Mbit QDR?II SRAM 2-word Burst 36-Mbit QDR?⑸I SRAM 2-word Burst 36-Mbit QDR垄芒II SRAM 2-word Burst	http:// Renesas Electronics Corporation
CY7C1525V18-200BZC CY7C1525V18-250BZC CY7C1514V18	72-Mbit QDR-IISRAM 2-Word Burst Architecture 8M X 9 QDR SRAM, 0.45 ns, PBGA165 72-Mbit QDR-IISRAM 2-Word Burst Architecture 72兆位QDR - II型⑩SRAM2字突发结	Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
CY7C1425AV18 CY7C1414AV18-167BZI CY7C1414AV18-167B	36-Mbit QDR-II SRAM 2-Word Burst Architecture 36-Mb QDR-II SRAM2-Word Burst结构36-Mb QDR-II SRAM2-Word Burst结构 36 - MB的QDR - II型的SRAM2字突发结构）6 - MB的QDR - II型的SRAM2字突发结构）	Cypress Semiconductor Corp.
CY7C1412BV18-167BZXI CY7C1414BV18-167BZXI	36-Mbit QDR-IISRAM 2-Word Burst Architecture 1M X 36 QDR SRAM, 0.5 ns, PBGA165	Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V	Renesas Electronics Corporation. Renesas Electronics, Corp.
CY7C1510V18-167BZXC CY7C1510V18-167BZXI CY7C1514V1	72-Mbit QDR-II垄芒 SRAM 2-Word Burst Architecture 72-Mbit QDR-II SRAM 2-Word Burst Architecture 72-Mbit QDR-II?SRAM 2-Word Burst Architecture	Cypress Semiconductor
CY7C1263V18-300BZI	36-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 18 QDR SRAM, 0.45 ns, PBGA165	Cypress Semiconductor, Corp.
R1QFA7218AB R1QCA7218AB R1QDA7218AB R1QCA7236AB R1	72-Mbit QDR II SRAM 4-word Burst	Renesas Electronics Corporation

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